Siemens’ new software can provide more insights into chip failure modes.
Siemens has released a new addition to its Tessent IC tool that gives designers more insight into hidden failure points in their own designs.
While shrinking feature sizes for digital circuits can improve performance per chip area, the reduced transistor dimensions can increase performance dependence on process variations. As we continue to inch toward sub-nm features, this reliance can introduce many different points of failure that could demand months of verification effort. Siemens claims its new tool can greatly accelerate this validation and enhance yield.
Designing to Improve Yield
Following a successful tapeout and delivery, engineers must not only ensure that their devices work as expected but must also find out how and why some chips fail.
To improve the yield of a tapeout (and therefore reduce costs), designers must ensure that their chips work under a variety of uncontrollable circumstances. If, for example, a small change in the substrate’s characteristics considerably reduces yield, engineers must pinpoint where in their design these failures occur. Without modern tests and modeling tools, this can be an extremely cumbersome task for circuits involving billions of transistors and thousands of different functional blocks.
As a result, modern IC design tools often incorporate different methods of hardening the end device against process variations. By unifying experimental measurements with simulated system results, designers can better understand their devices’ failure modes.
Hi-Res Chain: A Visual Into Chip-Level Failures
This is exactly the goal of Siemens’ newest Tessent feature, Hi-Res Chain software. Instead of providing a broad look at a device’s operation and failure modes, the Tessent Hi-Res Chain feature can provide “transistor-level isolation” to better identify defects and failure sources in a datapath. This not only improves the designer’s understanding of the system but also enables immediate corrective action to speed time to market.
By combining experimental test results with layout- and cell-aware simulation models, the Hi-Res Chain software can precisely pinpoint the location and mechanism of failures in both superficial and deep signal chains. Further coupled with Tessent’s AI features, the Hi-Res Chain software can make learning from failures a much faster process than traditional methods.
An 80% Success Standard
While designers working with larger feature sizes may still prefer traditional failure analysis techniques, the Hi-Res Chain software may aid in smaller featured devices with billions of transistors. The Hi-Res Chain software also meets Siemens’ 80% success standard, with over 80% of reports generated by Tessent confirmed through traditional failure analysis. This indicates that the software could be of great utility to verification and validation engineers.
Share to your social below!
